Conventional Radio Frequency (RF) wireless communication system receivers and transceivers receive an RF wireless signal—typically in the GHz frequency range—at one or more antennas. The received signal is processed by a receiver circuit including a Low Noise Amplifier (LNA), operative to amplify the antenna signal, and a down-conversion mixer operative to convert the RF signal to a much lower frequency, usually well below 100 MHz, by mixing it with a Local Oscillator (LO) signal. The receiver circuit additionally contains circuits and software functions implementing operations such as analog to digital conversion (ADC), amplification, filtering, and demodulation. In modern receivers, most or all receiver circuits are integrated into one or more integrated circuit (IC) chips.
FIG. 1 depicts a conventional down-conversion mixer 1. The down-conversion mixer 1 includes an RF mixer circuit 3 receiving an RF signal from a LNA 2. The RF mixer 3 additionally receives a synthesized LO signal. The LO signal is generated by an LO divider circuit 4, which divides the output of a frequency source, such as a Voltage Controlled Oscillator (VCO) 5.
The RF mixer 3 and LO divider 4 are balanced circuits, as indicated by the p and n notations in FIG. 1. As known in the art, a balanced circuit is one in which the reference voltage is not ground, but rather an inverted version of the signal itself. Balanced circuits thus include complementary (or “mirrored”) positive (p) and negative (n) portions. Balanced circuits improve signal quality by rejecting common-mode interference and noise, including that generated by component mismatches, temperature instability, and the like. When realized in integrated circuits, balanced circuits additionally require fewer via holes to reference a common ground voltage, and have lower parasitic inductance and capacitance. As also known in the art, RF receiver circuits divide RF signals into In-phase (I) and Quadrature (Q) components, which are offset in phase, e.g., by 90°. Both the RF mixer 3 and LO divider 4 include I and Q components operative to process the I and Q signal components. Since both the I and Q circuit components are balanced, both the RF mixer 3 and LO divider 4 generate four outputs, denoted herein (and indicated in FIG. 1) as Ip, In, Qp, and Qn.
The down-conversion mixer 1 determines some important performance parameters of the overall receiver. For example, the Image Rejection Ratio (IRR), the second order intercept point (IP2) and the LO feedthrough are strongly dependent on the balancing of the down-conversion mixer 1.
The circuits forming the RF mixer 3 and LO divider 4 include transistors and passive components. Effective balancing of the circuits is primarily determined by the matching of the devices therein. Small component mismatches can lead to large degradation of the IRR or the IP2 (or both). For example, a 2% mismatch in the components in the down-conversion mixer 1 degrades the IRR to 34 dB. If better IRR is required, calibration is conventionally performed to restore the balancing and achieve an IRR >40 dB. A similar effect is observed with respect to IP2, where target values are in excess of +50 dBm—indeed, some systems require IP2>+70 dBm.
Balance in the RF mixer 3 and LO divider 4 circuits may be influenced by physical layout of the circuits on an integrated circuit. In prior art designs, physical symmetry may be targeted on the RF mixer 3 and/or LO divider 4 block layout level, but is not considered in the combination of these two functions in the top-level layout. Furthermore, where the layout of prior art RF mixer 3 and/or LO divider 4 blocks may appear to exhibit physical symmetry (i.e., placement of components), they are not electrically symmetrical (i.e., when considering the flow of currents). In prior art layouts, RF current return loops—such as those between portions of the RF mixer 3 and LO divider 4—are relatively long, and are not electrically symmetric. Additionally, prior art RF mixer 3 and LO divider 4 circuit layouts experience high current consumption due to long interconnect lines. The increased interconnect capacitances must be charged and discharged at GHz frequency, requiring larger driver buffers, and draining more current.
Achieving acceptable balance in prior art receiver RF mixer 3 and LO divider 4 circuits is elusive, at least partially due to deficiencies in the physical layout of these circuit blocks.